1. Field of the Invention
The present invention relates to an information processing apparatus which is operated by a clock with a predetermined frequency, in particular to a clock control apparatus for controlling a clock of a cycle counter which stops an information processing apparatus using a plurality of clocks with different phases (for example, using a plurality of clocks with different phases which are internally or externally generated from a basic clock, a CPU (Central Processing Unit) can be internally operated by a clock with a frequency several times higher than the frequency of the basic clock).
2. Description of the Related Art
In developing an information processing unit which performs a pipeline process or the like, the unit should be effectively tested.
FIG. 1 is a schematic diagram for explaining the operation of a pipeline processing unit. As shown in the figure, the pipe line processing unit operates corresponding to commands in a pipeline. When a unit is developed, processes of commands are tested in time sequence.
In the figure, the pipeline processing unit executes commands C1 to C4 as they are. An error E1 (for example, a parity error) takes place in a process system which executes a command C5. When the error E1 takes place, a test unit stores the error information (E5) and sends it to an error analysis system (E2).
The error analysis system (E3) categorizes the received error information as several levels (such as a recoverable error, and a fatal error which results in the system going down). On receipt of the error information, the error analysis system causes all clocks to be stopped (E4).
In the example shown in FIG. 1, when all clocks are stopped (namely, at a command C13), the pipeline processing unit stops. While the command C5 was being processed, an error took place. Thus, just after that, all clocks of the unit should be stopped and the state before the command C5 has been processed should be held. However, as shown in FIG. 1, after a process for an error is performed, all clocks are stopped. Since several commands are executed during this period, process information of the command C5 is replaced with the subsequent command. Thus, the process information of the command C5 is lost.
In this case, a function which can immediately save process information of a command which caused an error to a register or the like is desired. However, if such a function were employed in the entire unit, the circuit scale would remarkably increase. To solve such a problem, a technique which uses a cycle counter is known. Next, the technique using the cycle counter will be described.
FIG. 2 is a schematic diagram for explaining a conventional cycle counter.
If the user cannot know at what command counted from the command start time an error took place, a particular value is loaded to the cycle counter. Then, commands are executed from the command start time and the cycle counter is started. As in the case shown in FIG. 2, "8" is loaded to the cycle counter. When all clocks are stopped (namely, the value of the cycle counter becomes zero), the unit checks whether or not error information is saved.
In the example shown in FIG. 2, since an error has taken place, a reset signal is issued to the unit. Thereafter, a value smaller than the last value is loaded to the cycle counter. For example, in the case shown in FIG. 2, "7" is loaded to the cycle counter. The same commands are reexecuted from the command start time and the cycle counter is started. Likewise, the unit checks whether or not error information is saved. These steps are repeated.
If a command which caused an error is known, it is not necessary to repeat such steps. In the example shown in FIG. 2, when "4" is loaded to the cycle counter, since no error takes place, it is found that the error took place in the command C5.
When the processing state of a command which caused an error can be saved with the above-described steps, the cause of the error is determined corresponding to the processing state.
FIG. 3 is a circuit diagram showing the construction of a conventional cycle counter. For the sake of simplicity, it is assumed that the cycle counter operates with a basic period clock t and a t/2 period clock.
FIG. 4 is a timing chart of signals in the conventional cycle counter. In the figure, units FF3 and FF4 to be tested are counters. The numbers of clock pulses of these under-test devices FF3 and FF4 are counted.
Next, the clock control by the conventional cycle counters will be described.
Before using the cycle counters, values with which clocks are stopped should be set. In the example shown in FIG. 3, with an external clock stop command m6, the basic period clock is stopped. The external clock stop command m6 is issued by the user, a machine check of the unit, or the CPU when any command is executed.
With the external clock stop command m6, at time a shown in FIG. 4, a flip-flop FF1 which stops the clock is set. By a gate G1, the basic period clock signal m1 which is output from a signal generator SG is suppressed while the flip-flop FF1 is being set (clock signal m12). In other words, when the flip-flop FF1 is set, a clock stop signal m2 becomes high ("1"), thereby turning off the gate G1 which is a NOR circuit. Thus, the output of the gate G1 becomes low.
The clock signal m12 is supplied to a gate delay circuit DL1 (such as a delay line which adds a predetermined delay period of time). In addition, the clock signal m12 is supplied to a NOR gate G3 and an inverter G2. A clock signal m4 which is the output of the gate delay circuit DL1 has a phase of t/2. For example, when the basic period is 20 ns, the phase of the clock signal m4 is 10 ns later than the clock signal m12. Thus, when the clock signal m4 is suppressed with the clock stop signal, it is stopped 10 ns later than the clock m12.
The counter FF3 which is a unit to be tested uses a clock signal m3. While the clock signal m3 is being suppressed, the counter FF3 stops. On the other hand, the counter FF4 uses a clock signal m3. The clock signal m5 is an OR result of the clock signal m12 and a clock signal m4 which is the output of the gate delay circuit DL1. The clock signal m5 is a clock signal with a period of 1/2t. Thus, the counter FF4 stops 10 ns later than the counter FF3 (at the time as shown in FIG. 4, the clock signal m3 which is supplied to the counter FF3 is stopped, whereas the clock signal m5 supplied to the counter FF4 is stopped one pulse later than the time a).
A cycle counter CYL comprises a flip-flop FF8 (which stores a count start command), a latch FF9, a decrementer D-1, a selector SEL1, and a decoder DEC. The output of the latch FF9 is connected to the input of the latch FF9 through the decrementer D-1 and the selector SEL1. When the selector SEL1 selects the output of the decrementer D-1, whenever the latch FF9 receives a fetch clock pulse, the value of the latch FF9 decrements by 1.
When the supplies of clock pulses to the FF3 and FF4 are stopped, predetermined data is selected by the selector SEL1. For example, cyclic value "5" is loaded to the latch FF9 of the cycle counter. Then, a start command m7 is input. Thereafter, the output of the decrementer D-1 is selected by the selector SEL1.
When the start command m7 becomes high ("1"), at time b (shown in FIG. 4), the flip-flop FF8 is set. A cycle counter enable signal m8 which is the output of the flip-flop FF8 becomes high. Thus, the cycle counter CYL starts a decrement operation. In addition, the clock stop flip-flop FF1 is reset and thereby the output m2 thereof becomes low. Thus, the gate G1 is turned on and thereby supplying the basic period clock signal m1.
With the above-described start command m7, the clock signals m3 and m5 which were stopped are supplied to the counters FF3 and FF4. Thus, the counters FF3 and FF4 of the under-test unit count their clock pulses. The counter FF3 of the under-test unit operates with the basic period (20 ns) clock signal. On the other hand, the counter FF4 operates with a t/2 period (10 ns) clock signal which is an OR result of the basic period clock signal (20 ns) and the output of the gate delay circuit DL1 which is later by 10 ns than the basic period clock signal. In other words, the counter FF4 performs a count operation at a speed twice as faster as that of the counter FF3.
When the latch FF9 of the cycle counter CYL becomes high ("1") at the time c (shown in FIG. 4), the decoder DEC adds a decode value "1" to the clock stop detecting circuit CSK. The clock stop detection circuit CSK causes the clock stop signal m10 to become high ("1"). With the high ("1") state of the clock stop signal m10, the clock stop flip-flop FF1 is set again thereby turning off the gate G1. Thus, the gate G1 suppresses the supply of the clock signal m1 and thereby stops the supplies of the clock signals m3 and m5.
At the same time, the cycle counter CYL becomes "0" and stops. The counter FF3 becomes "5" and stops. The counter FF4 becomes "10" and stops.
With the above-described operation of the cycle counter, the operation of the unit can be stopped at a desired position so as to obtain the state of an occurrence of an error.
However, since the cycle counter CYL counts cycles of the basic period clock signal (20 ns), the count value of the counter FF4 of the under-test unit becomes always twice the count value of the counter FF3. Thus, when there is a need to stop the counter FF4 at an odd number, even with an attempt to stop the supply of the clock signals with the cycle counter CYL, the counter FF4 stops at an even number. When the value of the counter FF4 is an odd number, the supplies of the clock signals cannot be stopped. Instead, after receiving one pulse of the t/2 period clock (10 ns), the counter FF4 is stopped.
For example, now assume that when the value of the counter FF4 is "9", a parity error of the counter takes place. At a time d shown in FIG. 4, one more pulse is supplied, because the t/2 period clock signal m5 (10 ns) is not stopped. Thus, the counter FF4 becomes "10" and stops. In this case, it is not clearly determined whether or not the error took place at the counter value "9" or "10". Thus, in the conventional circuit, when an error takes place in a circuit which operates with a t/2 period clock, the cause of the error cannot be completely determined.